//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

.const .align 16 .b8 params[384];

.visible .func  (.param .align 8 .b8 func_retval0[32]) __direct_callable__oxMain(
	.param .b32 __direct_callable__oxMain_param_0,
	.param .align 8 .b8 __direct_callable__oxMain_param_1[8]
)
{
	.reg .pred 	%p<8>;
	.reg .b16 	%rs<9>;
	.reg .f32 	%f<100>;
	.reg .b32 	%r<22>;
	.reg .b64 	%rd<45>;


	ld.param.u32 	%r2, [__direct_callable__oxMain_param_0];
	ld.param.f32 	%f1, [__direct_callable__oxMain_param_1];
	ld.param.f32 	%f2, [__direct_callable__oxMain_param_1+4];
	ld.const.u64 	%rd8, [params+8];
	cvta.to.global.u64 	%rd9, %rd8;
	mul.wide.u32 	%rd10, %r2, 12;
	add.s64 	%rd11, %rd9, %rd10;
	ld.global.s32 	%rd1, [%rd11];
	ld.global.s32 	%rd2, [%rd11+4];
	ld.global.s32 	%rd3, [%rd11+8];
	ld.const.u32 	%r1, [params+16];
	setp.gt.u32 	%p1, %r1, %r2;
	@%p1 bra 	$L__BB0_2;
	bra.uni 	$L__BB0_1;

$L__BB0_2:
	mov.f32 	%f96, 0f3F800000;
	bra.uni 	$L__BB0_3;

$L__BB0_1:
	sub.s32 	%r3, %r2, %r1;
	ld.const.v2.u64 	{%rd12, %rd13}, [params+32];
	cvta.to.global.u64 	%rd16, %rd12;
	mul.wide.u32 	%rd17, %r3, 4;
	add.s64 	%rd18, %rd16, %rd17;
	ld.const.u64 	%rd19, [params+24];
	cvta.to.global.u64 	%rd20, %rd19;
	shl.b64 	%rd21, %rd1, 3;
	add.s64 	%rd22, %rd20, %rd21;
	ld.global.v2.f32 	{%f16, %f17}, [%rd22];
	shl.b64 	%rd23, %rd2, 3;
	add.s64 	%rd24, %rd20, %rd23;
	ld.global.v2.f32 	{%f20, %f21}, [%rd24];
	shl.b64 	%rd25, %rd3, 3;
	add.s64 	%rd26, %rd20, %rd25;
	ld.global.v2.f32 	{%f24, %f25}, [%rd26];
	mov.f32 	%f28, 0f3F800000;
	sub.f32 	%f29, %f28, %f1;
	sub.f32 	%f30, %f29, %f2;
	mul.f32 	%f31, %f1, %f20;
	mul.f32 	%f32, %f1, %f21;
	fma.rn.f32 	%f33, %f30, %f16, %f31;
	fma.rn.f32 	%f34, %f30, %f17, %f32;
	fma.rn.f32 	%f35, %f2, %f24, %f33;
	fma.rn.f32 	%f36, %f2, %f25, %f34;
	abs.f32 	%f37, %f35;
	cvt.rmi.f32.f32 	%f38, %f37;
	sub.f32 	%f39, %f37, %f38;
	abs.f32 	%f40, %f36;
	cvt.rmi.f32.f32 	%f41, %f40;
	sub.f32 	%f42, %f40, %f41;
	ld.global.u32 	%r4, [%rd18];
	shr.u32 	%r5, %r4, 16;
	cvta.to.global.u64 	%rd27, %rd13;
	shl.b32 	%r6, %r4, 4;
	cvt.u64.u32 	%rd28, %r6;
	and.b64  	%rd29, %rd28, 1048560;
	add.s64 	%rd30, %rd27, %rd29;
	ld.global.v2.u32 	{%r7, %r8}, [%rd30];
	cvt.rn.f32.u32 	%f43, %r7;
	mul.f32 	%f44, %f39, %f43;
	cvt.rzi.u32.f32 	%r11, %f44;
	cvt.rn.f32.u32 	%f45, %r8;
	mul.f32 	%f46, %f42, %f45;
	cvt.rzi.u32.f32 	%r12, %f46;
	mad.lo.s32 	%r13, %r7, %r12, %r11;
	cvt.u64.u32 	%rd31, %r13;
	ld.global.u64 	%rd32, [%rd30+8];
	add.s64 	%rd33, %rd32, %rd31;
	ld.u8 	%r14, [%rd33];
	and.b32  	%r15, %r5, %r14;
	setp.eq.s32 	%p2, %r15, 0;
	selp.f32 	%f96, 0f00000000, 0f3F800000, %p2;

$L__BB0_3:
	cvt.u32.u64 	%r16, %rd1;
	ld.const.u64 	%rd34, [params];
	cvta.to.global.u64 	%rd4, %rd34;
	mul.wide.s32 	%rd35, %r16, 32;
	add.s64 	%rd36, %rd4, %rd35;
	add.s64 	%rd5, %rd36, 24;
	ld.global.v2.f32 	{%f98, %f49}, [%rd36+24];
	setp.geu.f32 	%p3, %f98, 0f00000000;
	ld.const.u32 	%r17, [params+340];
	setp.ne.s32 	%p4, %r17, 0;
	or.pred  	%p5, %p3, %p4;
	@%p5 bra 	$L__BB0_6;

	div.rn.f32 	%f50, %f98, 0f41200000;
	cvt.rzi.s32.f32 	%r18, %f50;
	neg.s32 	%r19, %r18;
	ld.const.u64 	%rd37, [params+224];
	cvta.to.global.u64 	%rd38, %rd37;
	mul.wide.s32 	%rd39, %r19, 16;
	add.s64 	%rd40, %rd38, %rd39;
	ld.global.f32 	%f51, [%rd40+8];
	setp.geu.f32 	%p6, %f51, 0f00000000;
	@%p6 bra 	$L__BB0_6;

	mov.f32 	%f96, 0f00000000;

$L__BB0_6:
	cvt.u32.u64 	%r20, %rd2;
	mul.wide.s32 	%rd41, %r20, 32;
	add.s64 	%rd42, %rd4, %rd41;
	add.s64 	%rd6, %rd42, 24;
	cvt.u32.u64 	%r21, %rd3;
	mul.wide.s32 	%rd43, %r21, 32;
	add.s64 	%rd44, %rd4, %rd43;
	add.s64 	%rd7, %rd44, 24;
	setp.lt.f32 	%p7, %f49, 0f00000000;
	@%p7 bra 	$L__BB0_8;
	bra.uni 	$L__BB0_7;

$L__BB0_8:
	add.f32 	%f99, %f49, 0f3F800000;
	mov.f32 	%f67, 0f3F800000;
	sub.f32 	%f68, %f67, %f1;
	sub.f32 	%f97, %f68, %f2;
	bra.uni 	$L__BB0_9;

$L__BB0_7:
	ld.global.v2.f32 	{%f53, %f54}, [%rd6];
	ld.global.v2.f32 	{%f55, %f56}, [%rd7];
	mov.f32 	%f58, 0f3F800000;
	sub.f32 	%f59, %f58, %f1;
	sub.f32 	%f97, %f59, %f2;
	mul.f32 	%f60, %f1, %f53;
	mul.f32 	%f62, %f1, %f54;
	fma.rn.f32 	%f63, %f97, %f98, %f60;
	fma.rn.f32 	%f64, %f97, %f49, %f62;
	fma.rn.f32 	%f98, %f2, %f55, %f63;
	fma.rn.f32 	%f99, %f2, %f56, %f64;

$L__BB0_9:
	ld.global.f32 	%f69, [%rd5+-12];
	ld.global.f32 	%f70, [%rd5+-8];
	ld.global.f32 	%f71, [%rd5+-4];
	ld.global.f32 	%f72, [%rd6+-12];
	mul.f32 	%f73, %f1, %f72;
	ld.global.f32 	%f74, [%rd6+-8];
	mul.f32 	%f75, %f1, %f74;
	ld.global.f32 	%f76, [%rd6+-4];
	mul.f32 	%f77, %f1, %f76;
	fma.rn.f32 	%f78, %f97, %f69, %f73;
	fma.rn.f32 	%f79, %f97, %f70, %f75;
	fma.rn.f32 	%f80, %f97, %f71, %f77;
	ld.global.f32 	%f81, [%rd7+-12];
	ld.global.f32 	%f82, [%rd7+-8];
	ld.global.f32 	%f83, [%rd7+-4];
	fma.rn.f32 	%f84, %f2, %f81, %f78;
	fma.rn.f32 	%f85, %f2, %f82, %f79;
	fma.rn.f32 	%f86, %f2, %f83, %f80;
	mul.f32 	%f87, %f85, %f85;
	fma.rn.f32 	%f88, %f84, %f84, %f87;
	fma.rn.f32 	%f89, %f86, %f86, %f88;
	sqrt.rn.f32 	%f90, %f89;
	rcp.rn.f32 	%f91, %f90;
	mul.f32 	%f92, %f86, %f91;
	mul.f32 	%f93, %f85, %f91;
	mul.f32 	%f94, %f84, %f91;
	st.param.f32 	[func_retval0+0], %f94;
	st.param.f32 	[func_retval0+4], %f93;
	st.param.f32 	[func_retval0+8], %f92;
	st.param.f32 	[func_retval0+16], %f98;
	st.param.f32 	[func_retval0+20], %f99;
	st.param.f32 	[func_retval0+24], %f96;
	ret;

}
	// .globl	oxMain
.visible .entry oxMain()
{
	.reg .b64 	%rd<2>;


	mov.u64 	%rd1, __direct_callable__oxMain;
	// begin inline asm
	// end inline asm
	ret;

}

